Semiconductor die edge is a susceptible region to failure due to high package-to-Silicon interaction stress, direct exposure of semiconductor die edge to environment or interface with other materials, and manufacturing defects. Among the manufacturing defects, die chipping or cracking is a known reliability risk and adds to the cost of manufacturing processors on die. Die chipping or cracking at die edges may be caused by a number of reasons including laser processing, wafer sawing, die handling during assembly and test etc. FIG. 1 illustrates an apparatus 100 with a Edge Die Monitor (EDM) to detect failures or defects including those caused by cracks or chips near the edges of a die.
Apparatus 100 comprises a semiconductor die 101, wire 102, and electro-static discharge (ESD) unit 103. Wire 102 and ESD unit 103 form the EDM. Wire 102 is laid around the periphery of die 101 in an active area 104 such that it surrounds the processor active area 105. Wire 102 has an input port “In” and an output port “Out,” where ESD unit 103 is coupled near the input port “In.”
When voltage and current is applied to the input port “In” then the output port “Out” is monitored. The output port “Out” may be coupled to a ground node. If no current or too much current reaches the ground node at output port “Out,” the EDM indicates that there is a fault in die 101 along wire 102. However, this information is not sufficient to identify where the fault in die 101 resides. Manual checks, that may take days and have low success rate, are performed to identify the crack/chip location(s) in die 101. Such manual checking often leads to product line shut-down and delay time-to-market of the product (die 101). Such manual checking is a roadblock to the square-wave ramping of High Volume Manufacturing (HVM), and leads to huge volume loss in marketable products.